1. Field of the Invention
The present disclosure relates to a phase locked loop circuit, and more particularly, to a method and apparatus for detecting jitter of a phase locked loop without using a separate measurement device.
2. Discussion of the Related Art
Representative examples of a flat panel display for displaying an image using digital data include a Liquid Crystal Display (LCD) using liquid crystal, a Plasma Display Panel (PDP) using discharge of inert gas, and an Organic Light Emitting Diode (OLED) display using an organic LED.
The flat panel display includes a display panel for displaying an image using a pixel matrix, a panel driver for driving the display panel, and a timing controller for controlling the panel driver. The timing controller uses clocks for data input/output or various signal processing functions and includes a Phase Locked Loop (PLL) circuit in order to generate internal clocks synchronized with external clocks. The PLL circuit as well as the timing controller is necessarily used in a plurality of electronic circuits using clocks.
When an electronic circuit having a PLL circuit built-in therein is tested, a clock jitter amount of the PLL circuit is detected so as to judge the reliability of the circuit or to judge jitter stability of a receiver circuit. However, in the related art, since the jitter amount of the PLL circuit built-in the electronic circuit is detected using a separate jitter measurement device, a test process was not efficient.